Using Timing Constraints For Generating At-Speed Test Patterns

The basic methodologies for creating at-speed test patterns are covered in numerous sources.2 While creating at-speed test patterns, it is important to account for timing exceptions and constraints such as false and multicycle paths. If these paths are not handled correctly during scan-based at-speed test pattern generation, it can lead to lower test quality and failing good chips on the tester, which reduce product yield.